Download e-book for kindle: 3D Microelectronic Packaging: From Fundamentals to by Yan Li, Deepak Goyal

By Yan Li, Deepak Goyal

ISBN-10: 3319445847

ISBN-13: 9783319445847

ISBN-10: 3319445863

ISBN-13: 9783319445861

This quantity presents a accomplished reference for graduate scholars and pros in either academia and at the basics, processing info, and functions of 3D microelectronic packaging, an development for destiny microelectronic applications. Chapters written by way of specialists disguise the newest study effects and development within the following components: TSV, die processing, micro bumps, direct bonding, thermal compression bonding, complicated fabrics, warmth dissipation, thermal administration, thermal mechanical modeling, caliber, reliability, fault isolation, and failure research of 3D microelectronic applications. quite a few photos, tables, and didactic schematics are incorporated all through. This crucial quantity equips readers with an in-depth knowing of all facets of 3D packaging, together with packaging structure, processing, thermal mechanical and moisture similar reliability matters, universal disasters, constructing parts, and destiny demanding situations, delivering insights into key components for destiny study and improvement.

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Extra resources for 3D Microelectronic Packaging: From Fundamentals to Applications

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McCauley, P. W. Nelson, D. Pantuso, P. Reed, J. Rupley, S. Shankar, J. Shen, C. Webb, Die stacking (3D) microarchitecture. Paper presented at the 39th annual IEEE/ACM international symposium on microarchitecture (MICRO’06) 2006 28. M. H. Ozguz, 3D system architectures, in Intelligent Integrated Microsystems, ed. A. C. Wolper, Proc. of SPIE 6232 6232K (2006). 667381 29. P. Jacob, O. Erdogan, A. M. P. F. McDonald, Predicting the performance of a 3D processor-memory chip stack. IEEE Des. Test Comput.

H. Ikeda, Heterogeneous 3D stacking technology developments in ASET, in CPMT Symposium Japan, 2012 2nd IEEE, 2012, pp. 1–4. 6523453 51. B. Y. C. H. B. C. S. C. H. F. A. C. C. Y. C. F. H. J. Y. C. P. H. Yu, High-aspect ratio through silicon via (TSV) technology, in 2012 Symposium on VLSI Technology Digest of Technical Papers, pp. 173–174 52. P. Lindner, V. Dragoi, T. Glinsner, C. Schaefer, R. Islam, 3D interconnect through aligned wafer level bonding, in Proceedings of the 52nd Electronic Components and Technology Conference (ECTC), pp.

After the entire die stack is mounted on a package, it is functionally tested. , cost of probing die on a wafer needs to be balanced against the cost of package waste and need for additional test steps later in the flow) and test coverage (while checking a greater degree of die functionality before packaging is financially viable, it can also require more sophisticated Sort technology). 13 One of the key considerations in manufacturing costs is the time it takes to test units. The greater the amount of time, the lower the throughput and hence higher the costs.

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3D Microelectronic Packaging: From Fundamentals to Applications by Yan Li, Deepak Goyal

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